I2S RX configure register
| RX_RESET | Set this bit to reset receiver |
| RX_FIFO_RESET | Set this bit to reset Rx AFIFO |
| RX_START | Set this bit to start receiving data |
| RX_SLAVE_MOD | Set this bit to enable slave receiver mode |
| RX_MONO | Set this bit to enable receiver in mono mode |
| RX_BIG_ENDIAN | I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. |
| RX_UPDATE | Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. |
| RX_MONO_FST_VLD | 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. |
| RX_PCM_CONF | I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & |
| RX_PCM_BYPASS | Set this bit to bypass Compress/Decompress module for received data. |
| RX_STOP_MODE | 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. |
| RX_LEFT_ALIGN | 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. |
| RX_24_FILL_EN | 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. |
| RX_WS_IDLE_POL | 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. |
| RX_BIT_ORDER | I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. |
| RX_TDM_EN | 1: Enable I2S TDM Rx mode . 0: Disable. |
| RX_PDM_EN | 1: Enable I2S PDM Rx mode . 0: Disable. |